FPGA Design Validation Engineer

Piper Companies is seeking a highly experienced FPGA Verification Engineer who can create and efficiently maintain testbenches in verification environments for hardware in electronic systems. The ideal FPGA engineer will be onsite 5 days a week in San Jose, CA .

Requirements for the FPGA Verification Engineer include:

Able to work on multiple projects or tasks in parallel while prioritizing tasks

Independently develop test plans, test sequences, and collaborate with designers to debug failures

Advanced understanding for verify integrated circuits and IP integrations

Been a part of the pure verification process for ASIC/FPGA projects

Experience working with other hardware engineers and RTL designers

Qualifications for the FPGA Verification Engineer include:

7-8 years of experience with verification in ASIC/FPGA

Proficient in SystemVerilog with OOP concepts

Previously developed object-oriented testbench infrastructures, BFMs, and testcases being in UVM

Experience with slow speed interface such as 12C, SPI, MDIO

Ethernet and PCIe experience

Advanced ability to script; Perl, Python, etc

RTL design experience

Has verified IP integrations, strategies and corner cases

Bachelor's degree in electrical engineering

Compensation for the FPGA Verification Engineer include:

Salary range: $140,000 - $165,000

Comprehensive benefit package; Medical, Dental, Vision, 401k match plus PTO, Sick leave as required by law, and Paid Holidays

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