We’re hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to life. About Us. Mythic is building the future of AI computing with breakthrough analog technology that delivers 100× the performance of traditional digital systems at the same power and cost. This unlocks bigger, more capable models and faster, more resp...
LOCATION. On-site 5 days/week in Chandler AZ - LOCAL PREFERRED. DURATION. 6 Month Contract to Start. Design Verification Engineer. Role Overview. We are looking for an experienced DV Engineer to join the full-chip verification team working on one of the world’s largest and most advanced scientific / supercomputing SoCs – a many-thousand-core, RISC-V-based processor targeted at exascale-class HPC and AI workloads. This is a true “cradle-to-grave” ...
Introduction to the job. We are looking for a Design Verification Engineer to serve as a technical leader driving verification strategy and execution for highly complex FPGA designs. This role will architect advanced verification environments, define methodologies, and ensure best-in-class quality for ASML's EUV Source systems. It requires deep technical expertise, leadership in verification practices, and the ability to influence design and veri...
ASIC/FPGA Design Verification Engineer. 100% Onsite. Mesa, AZ/Plano, TX/Hazelwood, MO. 6 Months (Possible extension or Conversion). $75-100.00/hr W2. Work statement is a non-managerial role, non-leadership role. AvionX has an exciting opportunity UVM Advance Verification FPGA Contractor at Lead or Senior level to join us as part of our **** Digital Avionics team. This position will also be considered for conversion from contractor to **** direct ...
Location – Santa Clara, CA. Job Responsibilities. Architect and develop verification environment, testbench components, and reference models for designs at block and system level. Develop a comprehensive test plan and implement test cases. Verify design in block and chip-level environments using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification. Perform RTL code coverage, assertion...
Job Details. Are you interested in working with the World s leading AI-powered Quality Engineering Company. Ready to advance your career, team up with global thought leaders across industries and make a difference every day. Join us at Qualitest. . We are looking for a Design Verification Engineer to join our growing team in Sunnyvale, CA United States. Job Description. Ensure the functional correctness, performance, and adherence to specificatio...
Title: Design Verification Engineer. Location: Phoenix, AZ (3 days in office). Type: W2 only. Job Description. You Are. An experienced SoC Design Verification Engineer able to provide design verification services for multi. CPU/DSP SoC. The Work. Testbench development - System Verilog UVM and C tests. Integration/development of C tests/APIs and SW build flow. Integration/development of UVM mailboxes and HW/SW communication components. Tes...
Job Overview. Ensure functional correctness, performance, and compliance with specifications for complex digital ASIC Core/IP designs. This role emphasizes deep, unit, and core-level verification. Key Responsibilities. Plan. Develop comprehensive Core Verification Plans based on micro-architecture and design specifications. Develop. Architect and implement reusable, robust verification environments using. SystemVerilog/UVM. . Test. Create and exe...
Reports To. VP of Engineering. Location. Fremont, CA (on-site only). Job Overview. Our Engineering team is seeking a Design Verification Engineer to join our onsite team and work closely with our design group. In this role, you will develop UVM-based verification environments, create and execute tests for digital and mixed-signal designs, and drive block- and subsystem-level verification. You’ll collaborate with RTL and mixed-signal engineers, ru...
About The Team. OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also...
