IC Physical Design Engineer

Job Description:

1. IC physical design signoff of 6nm/4nm/3nm and below world leading advanced process chip
2. Doing STA/TECO or IR/EM signoff & fixing of block and SoC level design
3. Coordination on the signoff and fixing tasks together with frontend team and physical design team for the complicated hierarchical chip (more than 20 million instances plus 1000 macros)
4. Signoff flow development to enhance project execution efficiency

Job Requirements:

• Bachelor's or Master's Degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
• 2-5 years of experience in IC design, physical design, or timing signoff.
• Strong knowledge of IC design, with tapeout experience considered a plus.
• In-depth expertise in IR/EM analysis, STA/TECO, and related EDA tools.
• Proficient in UNIX/LINUX environments.
• Skilled in at least one of the following programming languages: C/C , Python, TCL, Perl.
• Excellent communication skills and strong teamwork spirit.
• Ability to coordinate with multiple teams to resolve gating items and ensure timely completion of tasks.
• Capable of driving the team to deliver high-quality results on time.