Design Verification Engineer

Beaverton,Oregon,United States

Hardware

At Apple, we work every single day to craft products that enrich peoples lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a visionary and unusually talented Design Verification Engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apples customers every single day. Do your lifes best work here at Apple! This role is for a DV engineer who will enable bug-free first silicon for the IP Designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

**Description**

In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures. Develop block, IP and SoC level test-benches. Track and report DV progress using a variety of metrics, including bugs and coverage. Develop IP simulation environment, and work closely with analog team to ensure overall bug-free IP designs.

**Minimum Qualifications**

**Key Qualifications**

Deep proven understanding of SystemVerilog test-bench language and UVM

Shown experience developing scalable and portable test-benches

Validated experience with verification methodologies and tools such as simulators, waveform viewers, build/run automation, coverage collection, gate level simulations

Experience with IP verification methodology

Solid understanding of UVM knowledge, C/C knowledge

Significant experience with DDR PHY or Controller

Deep knowledge of one of the scripting languages: Python, Perl, TCL

Deep knowledge of formal verification methodology

**Preferred Qualifications**

**Education & Experience**

BS degree in technical discipline with minimum 3 years of confirmed experience. Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

**Additional Requirements**

Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.Learn more about your EEO rights as an applicant. (https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf)

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Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race,color,religion,sex,sexual orientation,gender identity,national origin,disability,Veteran status,or other legally protected characteristics. Learn more about your EEO rights as an applicant (Opens in a new window) .

Apple will not discriminate or retaliate against applicants who inquire about,disclose,or discuss their compensation or that of other applicants. United States Department of Labor. Learn more (Opens in a new window) .

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