GPU Cache Hierarchy Design Verification Engineer

Austin,Texas,United States

Hardware

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Engineering group, youll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you will be responsible for crafting and building the technology that fuels Apples devices. Together, we will enable our customers to do all the things they love with their devices. The GPU Cache Design Verification Engineer is responsible for the pre-silicon RTL verification of cache hierarchy and related units in a low power GPU design. This includes deep understanding of the micro-architectural details of these units, interactions between the units, and the connection of the uarch to the larger architectural intent of the GPU. A strong computer architecture background, experience in cache and memory subsystem verification, software engineering skills, and a proven foundation in verification methodology will be used to close testing coverage with high confidence.

**Description**

As a GPU Cache Hierarchy Design Verification Engineer, you will be responsible for: - Testing of major features and collaborating with other block and core level engineers to ensure flawless verification flow - Developing verification plans in coordination with design leads and architects - Architecting, building and maintaining verification test bench components and environments to validate architectural correctness of the design - Generating directed and constrained random tests - Running simulations and debugging design and environment issues - Crafting functional coverage points, analyze coverage, and enhance test environment to target coverage holes - Creating automated verification flows for block verification - Applying knowledge of hardware description languages (VHDL/Verilog), hardware verification languages/frameworks (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs

**Minimum Qualifications**

**Key Qualifications**

Strong knowledge of computer and cache architecture

Experience developing a unit or subsystem testing environment is a plus

Experience with memory/cache sub-system micro-architecture, which could include multiple levels of cache, coherent interconnects, MMUs or related blocks is a plus

Expertise in creating software solutions utilizing object oriented programming concepts

Experience with verification and hardware description languages such as SystemVerilog, Verilog, and VHDL is a plus

Experience with a verification methodology such as UVM/OVM is a plus

Experience with HDL simulators and waveform viewers is a plus

Experience defining coverage space, writing coverage models, and analyzing results is a plus

Demonstrated success working under strict schedule deadlines with the ability to manage multiple priorities

Excellent interpersonal skills and ability to collaborate

GPU experience, especially in the cache/memory hierarchy area, is a plus

**Preferred Qualifications**

**Education & Experience**

Minimum requirement of BS degree

**Additional Requirements**

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