The Package Engineering function provides support, expertise, and insight to the Silicon device development team through preliminary activities of package selection, packaging routing techniques, and necessary modeling and simulation work. The position involves diverse responsibilities, including evaluation of new packaging technology, package recommendation for custom devices, substrate design support, and device/package qualification.

This position requires experience in the Fabless semiconductor model with a broad knowledge of packaging technology and manufacturing. Successful candidates will have a deep understanding of a variety of IC package technologies.

Candidate should possess specific experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge of Chiplet technology, Optical integrated packages, and experience in extracting/simulating package designs for SI and PI using tools such as HFSS, ADS, POWER SI, and other leading tools.

Education

• Bachelor’s degree in Electrical Engineering, or other semiconductor packaging related discipline
• MS is preferred
• 8 to 10 years of experience in semiconductor packaging design, modeling, and simulations
• Good experience with signal and power integrity tools (SI/PI tools) for package level extraction/simulation
• Ability to work with Package Layout engineers
• Strong presentation and communication skills

Preferred

• Hands on package design; high-speed SI and PI, die and package decoupling caps optimizations, package and PCB SI and PI Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designs
• Hands on high-speed package and PCB design: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verification
• Packaging high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec, or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnect
• Hands on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designs
• Routing analyst, chip bumps analyses and package ball analyses
• Package material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constant
• PCB material characterization frequency dependent; routing degree of freedom
• Time domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signaling
• Time domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6
• Bathtub curve and BER analyses of high speed signaling
• DDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnections
• Clock jitter analyses, routing, clock tree analyses
• Simulating multi-physics electro-thermal analysis
• Collateral packaging manufacturing and assembly rules
• Chip and package Reliability analyses
• Die Pkg pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc.
• IR drop, and CPM (chip power model) die model using Redhawk and other tolls

Benefits:

401(k)

401(k) matching

Dental insurance

Employee assistance program

Flexible spending account

Health insurance

Health savings account

Life insurance

Paid time off

Referral program

Vision insurance