technology leader in the research and development of GPS (Global Positioning System) related hardware and software, including specialized receivers, anti-jam systems and other advanced products for government and commercial markets. Our ongoing work in high performance anti-jam GPS solutions and integrated communication / navigation systems continues to create career opportunities for talented individuals interested in the development of these cutting edge technologies. R&D focus includes GPS/INS systems, adaptive space-time antenna control techniques, data link receivers, attitude determination and control systems, and wireless communication systems. As this position requires the ability to obtain a DoD Security Clearance, US Citizenship is required.

Responsibilities:

• Architecting, designing, implementing, validating and integrating Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA) logic designs including interface logic, control logic and digital signal processing (DSP) in support of ongoing GPS Anti-Jam development efforts.
• Authoring and maintaining ASIC / FPGA design specifications and test-plans.
• Working closely with Design Verification Engineers, System Engineers, Software Engineers and Digital Hardware Engineers in the implementation, integration and testing of digital signal processing (DSP) in the target hardware.

Minimum Requirements:

• US Citizenship and the ability to obtain a DoD Security Clearance
• Minimum B.S degree in Electrical Engineering, Computer Science or a related field
• 8 years of experience (post BS degree) or 5 years of experience (with MS degree) in ASIC or FPGA design
• ASIC or FPGA or RTL design experience using System Verilog, Verilog or VHDL (System Verilog or Verilog preferred)
• ASIC/FPGA SoC design skills with understanding of ASIC or FPGA tools and flows.
• ASIC experience with Cadence or Synopsys tools or FPGA experience with Xilinx, Altera and/or Actel devices and flows.
• Experienced with simulation tools such as Questa from Mentor
• Hands on knowledge of high speed timing and timing closure
• Familiarity of ARM processors and AMBA bus protocols
• Working knowledge of digital designs including state machines, FFTs, and DDCs and high-speed digital I/Os such as DDR3, I2C and SPI
• Knowledge of basic signal processing concepts (MATLAB), implementing signal processing algorithms and positioning / navigation systems desired
• CVS version control tool experience a plus
• Previous experience related to military/aerospace design techniques