Senior Design Verification Engineer Austin TX (Hybrid role)

Life at Capgemini

Capgemini supports all aspects of your well-being throughout the changing stages of your life and career. For eligible employees, we offer:

• Flexible work
• Healthcare including dental, vision, mental health, and well-being programs
• Financial well-being programs such as 401(k) and Employee Share Ownership Plan
• Paid time off and paid holidays
• Paid parental leave
• Family building benefits like adoption assistance, surrogacy, and cryopreservation
• Social well-being benefits like subsidized back-up child/elder care and tutoring
• Mentoring, coaching and learning programs
• Employee Resource Groups
• Disaster Relief

About Capgemini Engineering

World leader in engineering and R&D services, Capgemini Engineering combines its broad industry knowledge and cutting-edge technologies in digital and software to support the convergence of the physical and digital worlds. Coupled with the capabilities of the rest of the Group, it helps clients to accelerate their journey towards Intelligent Industry. Capgemini Engineering has more than 55,000 engineer and scientist team members in over 30 countries across sectors including Aeronautics, Space, Defense, Naval, Automotive, Rail, Infrastructure & Transportation, Energy, Utilities & Chemicals, Life Sciences, Communications, Semiconductor & Electronics, Industrial & Consumer, Software & Internet.

Capgemini Engineering is an integral part of the Capgemini Group, a global leader in partnering with companies to transform and manage their business by harnessing the power of technology. The Group is guided every day by its purpose of unleashing human energy through technology for an inclusive and sustainable future. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, cloud and data, combined with its deep industry expertise and partner ecosystem. The Group reported 2023 global revenues of 22.5 billion.

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Disclaimer

Capgemini is an Equal Opportunity Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law.

This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodations do not pose an undue hardship.

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Job description:

We are looking for Senior DV Engineer who will define and write IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)

Key responsibilities:

• Writing stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed test cases.
• Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan.
• Writing SV (UVM) monitors, drivers, response checkers and SVAs for correctness.
• Debugging failing test cases to determine source of failure (tool, test case, checker, Verilog RTL) and track resolution.
• Collecting code and functional coverage results from random simulations and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage.

Required Skills

• Proficiency in Verilog, System Verilog, UVM coding skills required.
• Proficient in Verification skills (test planning, testcase, testbench, simulation, debug) required.
• Knowledge of ARM AMBA protocols a plus.
• Knowledge of LPDDR4/5 protocol a definite plus.
• Ability to work independently and in small teams without close supervision required.