Job Description:

We are seeking a highly skilled and experienced Senior DFT Design Engineer to join our team. The ideal candidate will have a strong background in Design-for-Test (DFT) methodologies, including scan, MBIST, ATPG, functional test, AMS test, and test compression. They should also possess expertise in relevant EDA DFT tools and validation and test time optimization. Additionally, experience with deep technology nodes, specifically TSMC N5 production test, would be highly valued.

ESSENTIAL DUTIES AND RESPONSIBILITIES:

1. Develop and implement DFT methodologies and strategies for complex digital designs in deep technology nodes.
2. Collaborate with design teams to define and implement DFT requirements from project inception to production.
3. Design, implement, and validate scan chains, compression techniques, and ATPG patterns for manufacturing tests.
4. Conduct fault coverage analysis and work towards achieving high test coverage goals.
5. Perform test vector generation, simulation, and verification for functional and structural tests.
6. Develop and optimize memory built-in self-test (MBIST) algorithms and memory repair strategies.
7. Collaborate with cross-functional teams to ensure proper integration of DFT features into the overall design.
8. Work closely with test engineers to define and validate test vectors and methodologies for production test.
9. Evaluate and select appropriate EDA DFT tools to support the DFT implementation flow.
10. Provide technical guidance and mentorship to junior DFT engineers.

QUALIFICATIONS:

1. Bachelor's degree in Electrical or Computer Engineering (advanced degree preferred).
2. Minimum of 10 years of industry experience in DFT design.
3. Extensive knowledge and hands-on experience with DFT methodologies, including scan, MBIST, ATPG, functional test, and test compression.
4. Proficiency in relevant EDA DFT tools (e.g., Synopsys DFT MAX, Mentor Tessent) and scripting languages (e.g., Tcl, Perl, Python).
5. Experience with AMS (analog/mixed-signal) test methodologies and validation.
6. Strong understanding of deep technology nodes, preferably TSMC N5 production test.
7. Solid understanding of test time optimization techniques and strategies.
8. Proven track record of achieving high fault coverage goals.
9. Excellent problem-solving skills and ability to analyze and debug complex DFT issues.
10. Strong communication and collaboration skills to work effectively within cross-functional teams.

Preferred Skills:

1. Experience with JTAG, IEEE 1500, or other boundary scan techniques.
2. Knowledge of post-silicon validation and debug techniques.
3. Familiarity with design verification methodologies, such as UVM.
4. Understanding of power-aware DFT techniques for low-power designs.
5. Familiarity with formal verification techniques for DFT.
6. Experience with design closure and physical design aspects related to DFT.
7. Knowledge of industry standards and trends in DFT methodologies.

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $170,000.00 - $195,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.