We are looking for Senior ASIC/RTL Design Engineer for our client in Santa Clara, CA

Job Title: Senior ASIC/RTL Design Engineer

Job Location: Santa Clara, CA

Job Type: Contract

Job Description:

Pay Range: $52.45hr - $75.97hr

Responsibilities:

• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
• Collaborate with architecture and hardware teams to understand the requirements.
• Work with verification and physical design teams to achieve high quality design and successful tape out.
• Design and implement logic functions that enable efficient test and debug.
• Participate in silicon bring-up for features owned.
• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
• Implement automation to increase design team efficiency.

Preferred Experience:

• Must have proven track record of ASIC design on several production tape-outs.
• Experience in Designing RTL block for an SOC.
• Experience in integrating ASIC IP into an SOC.
• Experience with Arm architecture and APB, AXI, CHI protocols.
• Experience with synthesis, static timing analysis & optimizations.
• Experience with design involving Interconnects.
• Experience writing timing constraints and exceptions.
• Experience with automation using scripting techniques such as PERL, Python or Tcl
• Ability to develop clear and concise engineering documentation.
• Experience in Power-saving techniques.
• Ability to organize and present complex technical information.
• Strong verbal and written communication skills.