Droisys is an innovation technology company focused on helping companies accelerate their digital initiatives from strategy and planning through execution. We leverage deep technical expertise, Agile methodologies, and data-driven intelligence to modernize systems of engagement and simplify human/tech interaction.

Amazing things happen when we work in environments where everyone feels a true sense of belonging and when candidates have the requisite skills and opportunities to succeed. At Droisys, we invest in our talent and support career growth, and we are always on the lookout for amazing talent who can contribute to our growth by delivering top results for our clients. Join us to challenge yourself and accomplish work that matters.

Client Description

Our client is a major Fortune 500 company and one of the world’s most innovative and cutting-edge technology companies, and this role is in the Interactive department.

Droisys is seeking ASIC RTL Design Engineer job offering Onsite Work for a long-term job opportunity in San Jose, CA area of the USA.

Position: ASIC RTL Design Engineer

Location: San Jose, CA (4 days a week onsite, Friday Optional Remote)

Duration: Long Term

KEY RESPONSIBILITIES:

• Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.

• Collaborate with architecture and hardware teams to understand the requirements.

• Work with verification and physical design teams to achieve high quality design and successful tape out.

• Design and implement logic functions that enable efficient test and debug.

• Participate in silicon bring-up for features owned.

• Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.

• Implement automation to increase design team efficiency.

PREFERRED EXPERIENCE:

• Must have proven track record of ASIC design on several production tape-outs.

• Experience in Designing RTL block for an SOC.

• Experience in integrating ASIC IP into an SOC.

• Experience with Arm architecture and APB, AXI, CHI protocols.

• Experience with synthesis, static timing analysis & optimizations.

• Experience with design involving Interconnects.

• Experience writing timing constraints and exceptions.

• Experience with automation using scripting techniques such as PERL, Python or Tcl

• Ability to develop clear and concise engineering documentation.

• Experience in Power-saving techniques.

• Ability to organize and present complex technical information.

• Strong verbal and written communication skills