ASIC Verification Engineer- UVM / RISC-V / System Verilog

We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking for Senior ASIC Verification Engineer to join their team in California on a remote basis.

If this is you please continue reading below!

Responsibilities:

• Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.
• SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation)
• Architect and implement complex RTL designs.
• Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.

Qualifications:

• 5 years of ASIC design experience, RTL logic Design
• Knowledge of ARM/MIPS/RISC-V Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
• Familiarity with AMBA/APB/AXI Protocol
• Familiarity with processor peripheral interfaces like SPI, eMMC, *MII, GPIO, I2C ....
• Excellent Verilog/System Verilog programming skills.
• Experience with UVM (or similar).

Keywords: UVM / ASIC /System Verilog / Verilog / Python / Perl/ RTL Design

If interested Apply via LinkedIn, or send your CV to fm@eu-recruit.com

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