Our client,a worldwide technology leader, is seeking a DFT Senior Staff engineer, to join their team. As a DFT engineer you will be part of the Silicon teams to document DFT specifications and define requirements. The ideal candidate will have 10-15 years experience with Synopsys TetraMAX, will be a USC or Green Card Holder, and be located near Phoenix, Arizona (preferred). Sorry no corp-to-corp contracts.
Job Title: Design-For-Test, Senior Staff Engineer
Location: Arizona or possibly remote for the right candidate!
Pay Range: $65hr -$89hr
Job Description:

• Collaborate with Silicon teams to document DFT specifications and define requirements.
• Develop and implement DFT architecture and infrastructure.
• Enhance and execute advanced DFX (DFT/Design-For-Debug) methodologies, focusing on debug support.
• Generate structural test vectors, analyze, and improve coverage, test time, and test cost.
• Execute DFT flow to implement and refine DFT solutions within hierarchical designs.
• Verify DFT implementation and PE pattern delivery through DFT flow execution.
• Address STA, physical, power, and logical issues impacting DFT in collaboration with designers.
• Collaborate with test engineers to bring up test vectors on silicon.
• Work with lab bring-up teams to implement test vectors in the lab environment.
• Manage schedules and support cross-functional/cross-organizational engineering efforts, both internally and externally.

Requirements:

• Minimum of ten plus years of experience in Hardware Design-For-Test (DFT) engineering.
• Experience with Synopsys DFT tools (Tetramax, TestManager, DFT Compiler, BSD Compiler, Formality, Spyglass/Advisor).
• Minimum of ten years of experience in silicon design and/or verification.
• Bachelor's Degree or equivalent (12 years) of work experience (Associates Degree with 6 years of work experience also acceptable).

Preferred Qualifications:

• Experience in developing DFT specifications.
• Proficiency with industry-standard DFT and design tools.
• Skills in debugging ATPG/MBIST patterns.
• Understanding of STA constraints and their interaction with DFT.
• Experience with Root Cause Analysis.
• Proficiency in IP/Top Scan and IP/Top Mbist insertion (all EDA solutions).
• Knowledge of scripting languages such as TCL, Perl, and Python.
• Familiarity with JTAG and IEEE standards 1149.1 and 1149.6.
• Experience with iJTAG IEEE 1687 standard.

Location:

• In-office position based in Phoenix, AZ (Relocation assistance available).

Comments:

Electronic Design Automation (EDA) (P3 - Advanced)

English (A1 - Elementary) Please apply today!
For a faster response please email me directly to: Tracey.Washburn@experis.com with a small summary of what makes you the perfect fit.
Best Regards,
Tracey Washburn
Key Accounts Recruiter
Experis Enterprise Non-IT
T: 1 919 702 9247
Tracey.Washburn@experis.com
www.experis.com
linkedin.com/in/tracey-washburn-250395228