Roles and Responsibilities:
What are the main functions of this role?
The Senior FPGA Digital Design Engineer will be a technical contributor with the focus on digital design of complex Field Programmable Gate Array (FPGA) designs used in space applications. This exciting position will be focused on FPGA design tasks, but may include FPGA verification tasks, depending on candidate's interest and experience.
Qualifications and Education Requirements:
Required Skill Sets:
o BS degree or higher in Electrical Engineering and 7 years detailed electronics design experience with at least 5 years of FPGA design experience (verification experience is a plus)
o Experience with design trades, design concept discussions, system specifications, system analyses and failure reporting.
o Exceptional written communication skills, strong presentation skills and the ability to contribute to technical group discussions and conversations with customers and team members
o Engineers who are interested in working on a small team of enthusiastic technical experts are encouraged to apply. This opportunity includes close mentorship with a technical expert
o Familiarity with clock domain crossing (CDC) tools and FPGA design pitfalls is nice to have.
o Familiar with AXI based design, DMA, and scripting tools.
o Experience with embedded processor-based electronics architecture.
o Strong interpersonal and self-leadership skills. We have a great team! Blue Canyon values people skills and technical competence working together.
o Related technical experience may be considered in lieu of education.
Desired Skill Sets:
o Works independently and with limited supervision to generate FPGA designs based on detailed design requirements using primarily VHDL
o Design and verify margin, compliance, and fault robustness of high-speed serial interfaces such as 10 Mb /100Mb/1Gb Ethernet, SpaceWire and LVDS interfaces using simulation methods such as UVM, OVM, or a functional test bench (module and system level)
o Capture requirements, create state diagrams, timing diagrams, and other design documentation as required by the design process
o Design robust Finite State Machines (FSMs) and interface logic
o Generate FPGA test vectors and simulation test benches, executing them in a verification environment such as ModelSim or QuestaSim
o Develop constraints for and synthesize FPGA designs using Client, Libero, Libero SoC, and Vivado tool suites
o Capable of chip-level and board-level debug in the lab with a variety of test equipment with supervision as needed
o Communicates design detail, issues, and concerns effectively in verbal and written form.
o We value enthusiasm and dedication toward developing highly integrated CubeSat and Blue Canyon Technologies FPGA design solutions and products
o Other responsibilities as assigned.
Years of Experience Required (if any): 7 or more
Education Level Required: BS or higher
How will the contractor's success be measured?: the contractor will be paired with a Lead EE who will provide feedback to both the contractor and the Dir. Of EE regarding said performance.