Principal Engineer -Memory Technology/Design Lead at Intel in Boise, Idaho, United States Job Description Job Description About the Technology Development Group: Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD's more than 13,000 employees drive breakthrough research, develop next generation process and packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Enablement (DE) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO) and delivers the Process Design Kits (PDKs) and Foundation IP (FIP) that designers need to support their product design work and fully leverage the technology. The Advanced Design (AD) team is part of Intel's DE Organization, and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DE is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies About the Role: As the Memory Technology/Design Lead, you will partner with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel's advanced CMOS process technologies. Responsibilities: Memory pathfinding activities and power, performance, area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement. Memory bit-cell and complex periphery IC layout and automation. Memory array/IP design, memory circuit innovation, test-chip design. Pre-Si verification, post-Si validation, and debugging to enable yield and parametric tracking/ramp. Internal and external customer engagement to enable optimized usage of Intel memory technology Required Experience/Knowl To view full details and how to apply, please login or create a Job Seeker account