As an ASIC Design Engineer with Forward Edge ASIC, you will be developing ASIC and FPGA designs that will be included in an array of complex, innovative and exciting products. Your responsibility will be developing RTL for both ASIC and FPGA design environments. You will benefit from the experience of highly qualified and experienced digital design engineers on the team. You will work closely with verification, analog design, physical design and architecture teams.

Responsibilities include, but are not limited to the following:

• Working within a large group of ASIC design engineers to deliver digital ASIC designs for FPGA and ASIC products.
• Writing detailed implementation plans and specifications for your ASIC design blocks.
• Writing Register Transfer Level (RTL) code using industry standard hardware description languages.
• Writing lower-level test bench code to verify baseline functionality and features for design blocks.
• Writing test plans and coordinating with the Design Verification team to fully verify design blocks.
• Synthesizing RTL code using industry standard tools and analyzing results.
• Providing RTL updates to meet Power, Performance and Area (PPA) requirements.
• Writing and executing plans for the post silicon lab validation.
• Providing continued support for design blocks working within a larger system level environment through productization and production.
• Process and methodology automation utilizing common scripting languages (i.e. python, perl, tcl).

Qualified Applicants will have the following education and experience:

• Bachelor’s or master’s degree in electrical or computer engineering. Preferred focus on digital design and/or computer architecture.
• Relevant prior experience working at this level as an ASIC Design Engineer is a plus.
• Experience with RTL coding languages is a plus.