Responsibilities

• Create top-down mixed-signal verification strategies for cutting-edge System-on-Chips (SoCs), ASICs, and IP blocks.
• These designs may include both high-speed digital circuits and sensitive analog/RF circuits.
• Develop automated test benches and tools for evaluating simulation results during top-down block verification.
• Utilize these test benches to perform actual verification work.
• Design tools that automatically generate verification reports and manage regression testing.
• Collaborate with analog and digital designers working on Verilog-A and behavioral models.
• Integrate these models into comprehensive system verification suites.
• Ensure the validity and optimize the performance of designer behavioral models.
• Verify correct usage of connect modules.
• Work closely with system architects to develop system tests.
• Stimulate the SoC from the IC boundary to ensure functionality across all data types and operational modes.
• Implement automatic regression for verification suites using Cadence AMS Designer verification flow in Xcelium

Must haves

• Holds a Master’s Degree in Electrical Engineering (EE) or Electronic and Computer Engineering (ECE).
• Possesses over 2 years of experience with an Analog Design Flow.
• Familiarity with tools such as Cadence Virtuoso, Incisive/Xcelium, AMS-Designer, Verilog-AMS, and Spectre.
• Skilled in modeling languages, including Verilog-A, Verilog-AMS, and SystemVerilog/UVM.
• Proficient in scripting languages such as Python, PERL, TCL, BASH/TCSH.
• Exposure to Matlab is beneficial.
• Knowledgeable in developing mixed-signal self-checking test benches for automatic regression.
• Comfortable working across both analog and digital design paradigms.
• Experience verifying ASICs with power gating and multiple clock and power domains is desirable.
• Possesses a general understanding of analog circuits and the ability to fit analog behavioral models.