About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

The Boise, ID / Morrisville, NC team is looking for a Senior Staff DFT engineer. This engineer will report into a team tasked with various DFT activities. One activity is design verification of DFT IP inserted at RTL level. This verification effort is UVM based. You will also participate in pattern development work and ATE bring-up activities. ICL/PDL is deployed across single chiplet or multi-chiplets. Engineers will spend time working on high-speed serial IO and DDR sub-systems. ATE bring-up work will require strong knowledge of electrical principles and is a great learning opportunity that allows developing a broader set of skills.

You may have had a solid career in DFT, perhaps focusing mostly on ATPG and MBIST activities, and desires to pursue other areas of DFT. Or may have had more exposure to ATE and wish to move into front-end DFT work. Or may already have experience in DFT RTL DV, functional patterns, and ATE work, and wish to perform more of the same at a different employer.

In this role you will be exposed to:

• UVM test case development when new DFT RTL is introduced into the design.Opportunity to learn DFT architecture given the requirement that underlying logic be thoroughly tested in RTL form.

• Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files which then allow developing design verification flows that can span a generation of designs.

• Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses.

• Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE. Like structured (ATPG/memory BIST) patterns, functional patterns leverage automation. A functional test pattern may load via JTAG or through a proprietary bus. In the end this functional pattern may interact directly with registers or load code into a processor resident in the DUT which then runs the test case. The complexity of these patterns requires that automated approaches be deployed to create them and to allow quicker regeneration.

• Debug of high speed IOs to include DDR and SERDES, working with designers, internal and third-party IP developers, to understand test requirements, help architect test access, verify the proper integration in the netlist, develop patterns, and support ATE bring-up and debug.

• DFT planning for 3D stacked devices.

• DFT planning for IP that cannot be probed at wafer, including HBM.

Above are a subset of activities this position will encounter. The team is geographically diverse. Our desire is to staff this position in our Boise, ID or Morrisville, NC office.

What We're Looking For

• Bachelor's degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience. Or Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.

• 3 Years of DFT related experience.

• Experience in one or more of the following is required: DFT including ATPG, memory BIST, design verification, JTAG/ICL/PDL, functional test, high-speed IO, DDR, multi-chiplet designs and ATE/bring-up of wafer and package.

• Show a pattern of greater and greater responsibility, including complete ownership of an activity.

• Demonstrate an ability to mentor junior engineers, devising ways and methods to enable them to grow in their careers.

• Demonstrate an ability to innovate to stay on schedule.

#LI-TM1

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.