You haven't searched anything yet.
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.What You Can Expect
The Boise, ID team is looking for a Senior Staff DFT Manager. This manager will oversee various DFT related activities.
Design verification of DFT IP inserted at RTL level. This verification effort is UVM based.
ATE functional pattern development.
ATE bring-up activities.
Architecture discussions.
High-speed IO, DDR, chip to chip, DFT due diligence
The ideal fit for this role has experienced many areas of DFT development. Previous managerial experience is preferred but not mandatory. If lacking previous direct hands-on management experience, consideration will be given to a someone with a history of technical leading a small team.
This role interfaces across the company with other DFT leads, Operations, and Planning. Areas of interest include strong planning skills, strong management ethics, experience dealing with project complications and setbacks, experience dealing with projects that change direction, experience dealing with large designs where the pre-tapeout due diligence is significant, experience dealing with complicated ATE bring-up at both at both wafer and package, RMA knowledge, system to ATE correlation, and understanding DFT architecture sufficient to drive test case development. The work area is broad, and the pace is quick. The ideal candidate is highly organized and able to fallback on best practices to motivate a team and keep projects on schedule.
What We're Looking For
To be successful in this role, you must:
Have a Bachelor's, Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or similar field.
Have 7 or more years of DFT related experience.
Have 2 or more years of DFT related management experience
Ideally have experience in all areas of DFT including ATPG, memory BIST, design verification, JTAG/ICL/PDL, functional test, high-speed IO, DDR, multi-chiplet designs and ATE/bring-up of wafer and package. All resumes with quality accomplishments in a subset of these disciplines will be reviewed, and the individual skills of the applicant will be considered.
Show a pattern of greater and greater responsibility, including complete ownership of an activity.
Demonstrate an ability to mentor junior engineers, devising ways and methods to enable them to grow in their careers.
Demonstrate an ability to innovate to stay on schedule.
#LI-TM1
Expected Base Pay Range (USD)
151,900 - 224,780, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Full Time
Semiconductor
$104k-129k (estimate)
06/06/2024
09/30/2024
SUNNYVALE, CA
<25
2020
DOLORES BETANCOURT
<$5M
Semiconductor