2 Senior Staff DV/UVM Engineer Jobs in Morrisville, NC
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Senior Staff DV/UVM Engineer
$126k-140k (estimate)
Full Time | Durable Manufacturing
1 Week Ago
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Marvell Technology is Hiring a Senior Staff DV/UVM Engineer Near Morrisville, NC
About MarvellMarvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactThe Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.
What You Can ExpectThe Boise, ID / Morrisville, NC team is looking for a Senior Staff DV engineer. This engineer will augment an already existing DV team within a DFT organization. The primary activity will be design verification, at block and full-chip, of DFT IP inserted at RTL level. This verification effort is UVM based. You may also participate in pattern development work. ICL/PDL is deployed across single chiplet or multi-chiplets and pattern development work will expose you to this technology. Engineers will spend time developing test cases for high-speed serial IO and DDR sub-systems. There will be opportunities to gain experience in other DFT areas if desired. A key requirement of this role is 3 years of working with UVM. While DFT skills are nice-to-have, the candidate wishing to grow their career would do well to join this team, continue their work in UVM based verification, while having the opportunity to develop skills in DFT.
In This Role You Will Work On
What We're Looking For
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation And Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your ImpactThe Custom and Compute Business Unit in Marvell is a world leader in advanced node semiconductor engineering. The team is developing high core-count AI compute platforms, 5G and 6G acceleration silicon, and custom ASIC designs for industry leading customers. Designs are large, complex, and challenge current design and manufacturing limits. Multi-die, 2.5D and 3D designs guarantee that Marvell remains at the forefront, delivering the highest and most integrated solutions that customers require.
What You Can ExpectThe Boise, ID / Morrisville, NC team is looking for a Senior Staff DV engineer. This engineer will augment an already existing DV team within a DFT organization. The primary activity will be design verification, at block and full-chip, of DFT IP inserted at RTL level. This verification effort is UVM based. You may also participate in pattern development work. ICL/PDL is deployed across single chiplet or multi-chiplets and pattern development work will expose you to this technology. Engineers will spend time developing test cases for high-speed serial IO and DDR sub-systems. There will be opportunities to gain experience in other DFT areas if desired. A key requirement of this role is 3 years of working with UVM. While DFT skills are nice-to-have, the candidate wishing to grow their career would do well to join this team, continue their work in UVM based verification, while having the opportunity to develop skills in DFT.
In This Role You Will Work On
- UVM test case development when new DFT RTL is added into a design. You will have the opportunity to gain experience in DFT architecture given the requirement that underlying logic be thoroughly tested in RTL form.
- Opportunities for script development where technical details of the underlying DFT architecture are abstracted into control files which then allow developing design verification flows that can span a generation of designs.
- Opportunity to work with JTAG, 1687, end evolving chiplet to chiplet test busses.
- Use of 1687 ICL/PDL to automate the creation of functional test patterns deployed on ATE. Like structured (ATPG/memory BIST) patterns, functional patterns leverage automation. A functional test pattern may load via JTAG or through a proprietary bus. In the end this functional pattern may interact directly with registers or load code into a processor resident in the DUT which then runs the test case. The complexity of these patterns requires that automated approaches be deployed to create them and to allow quicker regeneration.
- Debug of high speed IOs to include DDR and SERDES, collaborating with designers, internal and third-party IP developers, to understand test requirements, help architect test access, verify the proper integration in the netlist, develop patterns, and support ATE bring-up and debug.
What We're Looking For
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience, or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
- 3 Years of DV/UVM related experience.
- Experience in one or more of the following is required: System Verilog, UVM, Verification Test Plans, Coverage Driven Verification, Code Coverage, verification environments, test case simulation and debug.
- Because this role is within a DFT team, the applicant will benefit from having exposure to DFT concepts, including scan, memory BIST, functional testing, ATE, pattern generation and bringup on an ATE.
- Show a pattern of greater and greater responsibility, including complete ownership of an activity.
- Demonstrate an ability to mentor junior engineers, devising ways and methods to enable them to grow in their careers.
- Demonstrate an ability to innovate to stay on schedule.
The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation And Benefit ElementsAt Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Job Summary
JOB TYPE
Full Time
INDUSTRY
Durable Manufacturing
SALARY
$126k-140k (estimate)
POST DATE
09/02/2024
EXPIRATION DATE
09/08/2024
HEADQUARTERS
HAIDIAN, BEIJING
SIZE
200 - 500
FOUNDED
2004
CEO
MITCHELLLEEGAYNOR
REVENUE
$10M - $50M
INDUSTRY
Durable Manufacturing
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