Come aboard a pioneering hardware startup in Silicon Valley as a ASIC Design Engineer. The company mission is to revolutionize silicon by crafting Risc-V based computing platforms set to redefine the industry. Here, you'll collaborate with some of the globe's most talented and dedicated engineers, shaping designs that push the boundaries of performance, energy efficiency, and scalability. Offering an enjoyable, inventive, and adaptable work atmosphere, united by a shared ambition to develop products that will leave a mark on the world.

Actively seeking skilled UPF specialists to construct and validate power intent definitions at the IP/SOC level for cutting-edge, high-performance, power-efficient SOC designs. This pivotal role will drive forward a state-of-the-art power design initiative, collaborating across disciplines and playing a crucial role in expediting product launches.

Qualifications

We're in search of candidates with a solid background in ASIC design methodology, particularly focusing on power definition. Candidates should be well-versed in power intent definition, implementation, and verification workflows. Proficiency in the entire RTL2GDS flow (including RTL simulation, equivalence checking, synthesis, place and route, and intent validation) is essential. Successful candidates will be responsible for ensuring comprehensive coverage of power intent across static and dynamic checking methodologies. Additionally, they should comprehend the software and system-level interactions that influence power consumption.

Requirements

Candidates should be adept at initiating power intent checking workflows for new projects and proficient in scripting languages such as Tcl and Python.