Overview: 

Responsible for the design development and characterization of embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL etc.
Design and debug experience on RTL level signal synchronization, clock tree and cross domain clock designs is a significant plus.
Need to work closely with system and test engineers to develop high speed interface, package/board, and system clocks in image sensor and bridge chip products. 

Responsibilities: 

• Analog/Mixed-Signal design, simulation and verifications.
• High speed test with scope and BERT.
• Layout design and support. Need to get involved into layout optimizations for high speed or high precision performance directly.
• Interface verifications between analog and digital.
• IP and design spec documentations.

Requirements:  

• Familiar with Cadence analog design/layout flow and spice/spectreMDL simulations.
• Masters of Electrical Engineering or PhD with 4 yrs exp.

Annual base salary for this role in California, US is expected to be between $130,000 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.