Title: SoC (UVM) Verification Engineer
Location: San Jose, CA Onsite Required Start date: 8/5 or earlier Duration: 3 Months (possible extensions)

Hours: 40 hours per week
Scope:
Verification Engineer position is your opportunity to join one of the industry s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IoT
You will be responsible for RTL SoC/Subsystem verification of ARM based SoCs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows. You will report to the Director of Engineering (Verification).
KEY RESPONSIBILITIES
System level Verification
Execute functional test cases
Boot and test software/firmware on the SOC
Regression testing
Help develop test plan definition
Debugging/testing
Run simulations
Qualifications
UVM/SOC verification
SOC/CPU
System level Verification
Simulation in Synopsis VCS, Verdi
Review and write Firmware on SOC in C
Proficient in test plan definition and testcase development in C/Assembly/System Verilog
PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART