Qualifications
· Mentor junior engineers across multiple U.S. locations · Bachelor's Degree and 6 to 10 years work experience (or equivalent experience) · Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL · Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) · Proven track record of managing and executing to schedules, and driving tasks to closure · Candidates should also be comfortable multitasking because they may be asked to support multiple projects · Strong communication and documentation skills · Experience developing and implementing test plans · Ability to work effectively in a multi-site or borderless environment Responsibilities
· And now imagine doing that job while working in a fast-paced environment using state-of-the-art tools and methodologies, all the while increasing your knowledge, growing your skills, and advancing your career · Candidates will be given the opportunity to lead teams, mentor junior engineers, and contribute to the evolution of the company's verification processes and methodologies · Plan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL; · Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems; · Collect and analyze coverage metrics, then use that information to improve the effectiveness of test cases; · Enhance your leadership skills while leading small to medium sized DV teams · Create reusable Verification IP to be shared across the organization; · Drive changes to our process and methodologies · Enhance your DV skills as well as your knowledge of Electronic Warfare while working with subject matter experts;