1 Chief Chip Architect, AI Networking Job in San Francisco, CA

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Chief Chip Architect, AI Networking

Recruiting from Scratch

San Francisco, CA | Full Time

$201k-243k (estimate)

1 Month Ago

Chief Chip Architect, AI Networking

Recruiting from Scratch San Francisco, CA

$201k-243k (estimate)

Full Time 1 Month Ago

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Recruiting from Scratch is Hiring a Chief Chip Architect, AI Networking Near San Francisco, CA

Who is Recruiting from Scratch:

Recruiting from Scratch is a talent firm that focuses on placing the best candidate for our clients. Our team is 100% remote and we work with teams across the North America, South America, and Europe to help them hire.

Chief Networking Switch Chip Architect
We are looking for a Chief Networking Switch Chip Architect to take part in definition and implementation of our client's industry leading Networking Switch IC. You should be a highly motivated self-starter eager to solve real-world problems. This is a unique opportunity to help shape the future of AI Data Center Networking.

Responsibilities

Develop architectural specifications for next generation switch chips.
Provide technical leadership to a team comprising of Micro architects, and Performance modeling architects.
Work with the System/Software Architecture to ensure a streamlined multi-chip architecture.
Prior successful experience in architecting networking switches that achieved mass production is essential.
Perform architecture exploration and create detailed models for protocol processing engines.
Previous experience with Optical interfaces preferred.
Create protocol processing requirements from standards specifications.
Work cross functionally with Design team in defining and implementing the networking protocol functions in hardware.
Work with Design Verification team on unit-level and top-level functional verification and assist with pre-silicon and post-silicon validation activities.

Qualifications

MSEE with at least 15 years of experience, PhD EE preferred.
Knowledge of Ethernet switch architectures is essential.
Knowledge of Layer 2, Layer 3 and Layer 4 networking protocols is required (for example, Ethernet, IPv4/IPv6, TCP/UDP, RoCE, etc.).
Experience in designing scalable Layer 2 and Layer 3 packet processing engines, buffer management algorithms and scheduling/shaping is required.
Experience with micro-architectural specification of switch chips.
Strong software background to develop architecture models for next generation switches.

Location: Saratoga, CA

Salary: $200,000 - $280,000 base salary equity