Job Title: RTL Design Engineer

Work Location: Santa Clara, CA 95054

Duration: 12 Months

Work Type: Contract

Job Type: Onsite

Pay Rate: $70 .00-75.00/Hourly/W2

Overview:

TekWissen Group is a workforce management provider throughout the USA and many other countries in the world. This Client is an American multinational semiconductor company based in Santa Clara, California, that develops computer processors and related technologies for business and consumer markets. global company that specializes in manufacturing semiconductor devices used in computer processing. The company also produces flash memories, graphics processors, motherboard chip sets, and a variety of components used in consumer electronics goods.

JOB Description:

• Responsible for RTL design using Verilog HDL for implementation and debug. Read and comprehend System on Chip level architectural specification. Write microarchitecture specification for new and modified functions. Responsible for linting and simulation of design. Work with synthesis and backend teams for physical implementation. EDUCATION: Bachelor's or Master's in Computer Engineering

KEY RESPONSIBILITIES:

• Perform RTL design of digital components in Verilog/systemverilog.
• Analyze/fix Lint and CDC errors of the components.
• Guarantee quality/timely deliverables meeting project’s schedule.
• Help to improve/automate design process.

PREFERRED EXPERIENCE:

• Knowledge of RISK-V processor integration Express
• Multi-clock domain designs.
• Design constraints for synthesis and static timing analysis.
• Knowledge of AXI/AMBA protocol
• Knowledge of front-end RTL design tools and methodologies.
• Knowledge of scripting languages like Perl, tcl or cshell

TekWissen® Group is an equal opportunity employer supporting workforce diversity.