Location: San Jose, CA

Will transfer H1's.

Responsibilities:

• Micro-architecture specifications and participate in specification and test plan reviews.
• Architect and implement complex RTL designs.

Required Qualifications:

• 10 years of ASIC design experience with a demonstrable track record of RTL design
• Knowledge of ARM/RISC-V/MIPS Architectures, Memory hierarchy, Cache coherency, Virtual memory, Multicore CPU operation
• PCIE or CXL exp.
• B.S. (M.S. preferred) degree in Electrical or Computer engineering.