RTL Design Engineer
Looking for a solid RTL Design Engineer who has a strong background in supporting RISC-V houses. The primary technology will be focused around SOCs that are built around ML Accelerators. This person should have a solid background in RTL Design and also have an understanding of verification flows. This person should be a strong engineer and be able to come in and provide solid and consistent support with minimal hand holding or guidance.

Required
7 Years of RTL Design experience.
RISC-V Experience is a must have.
Strong Verilog experience.
Debug RTL/logic issues across various hierarchies (core, chip) in both pre-silicon and post-silicon environment. Environment will be pre-silicon.
Develop RTL as well as understand verification flows.
Understanding of SOC's that are built around machine learning accelerators.
Experience working out of companies such as - Groq, Nvidia, AMD, MAYBE Intel, etc.

Pluses:
Degree in Electrical Engineering, Electrical and Computer Engineering, Computer Engineering, Computer Science, or similar, with at least 5 years of industry experience.
GIT/BENDER experience.
Strong background and experience with high performance OOO CPU microarchitecture.
Experience working with an x86, ARM or RISC-V based CPU.
Architectural understanding of Rename, Scheduler, Reorder Buffer, and Datapath for an Out of Order CPU.

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description. All qualified applicants are welcome to apply.
Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.
Visit to contact us if you are an individual with a disability and require accommodation in the application process.

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