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Staff Design Verification Engineer

Aitopics
Wilmington, MA Full Time
POSTED ON 3/19/2025
AVAILABLE BEFORE 4/17/2025

Analog Devices

Analog Devices is a global leader in the design and manufacturing of analog, mixed signal, and DSP integrated circuits to help solve the toughest engineering challenges.

The Engineering Enablement team provides industry-leading tools, methodologies, and support to accelerate product development across the company. This position is part of the Systems Verification and Validation (SVV) team within the Engineering Enablement organization in the CTO Office. SVV is responsible for developing, adopting, and supporting tools, methodologies, and solutions across the entire DV landscape - including Unified Metric-Driven Verification (MDV), SystemVerilog (SV) / UVM-based methods, Mixed-Signal DV, Formal Verification, Functional Safety, Security, Portable Stimulus, and Emulation / Prototyping technologies.

The Role

We are looking for a highly skilled and motivated Staff Digital DV Engineer to join SVV as the lead for Digital DV methodologies. This person will soon become ADI’s go-to expert on all things SV / UVM, driving the adoption and optimization of these methods company-wide.

Key Responsibilities

  • Lead and champion the adoption of SV / UVM-based MDV methodologies, including spec analysis, vPlan creation, and SV assertion and coverage modeling to meet stringent verification closure metrics.
  • Contribute to ADI’s advanced Testbench Generator solution, helping to create unified, simulation-ready testbenches for IP and (sub)system-level verification in digital, DMS, and AMS domains.
  • Develop and support in-house UVM Verification IP (VIP) and integrate third-party VIP into ADI workflows and methodologies.
  • Enhance DV methodologies, leveraging AI / ML tools to optimize coverage and improve debugging productivity.
  • Collaborate closely with design teams to troubleshoot and resolve DV challenges in SV, UVM, and related areas.
  • Mentor and train junior engineers across the organization, helping to strengthen DV capabilities across teams.

Qualifications

  • Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science, with 7-10 years of relevant experience.
  • Deep expertise in SystemVerilog and UVM-based verification methodologies.
  • Strong automation skills using languages like Perl, Python, or similar.
  • Familiarity with communication protocols such as AMBA, I2C, SPI, and UART.
  • Experience with industry-standard digital simulators (e.g., Cadence Xcelium, Synopsys VCS).
  • Prior experience in DV of ARM / RISC-V processor-based subsystems (preferred).
  • Experience in Formal Verification (preferred).
  • Familiarity with Machine Learning applications in DV, especially for debug and coverage closure is a plus.
  • Strong communication skills, with the ability to clearly convey technical details to both peers and product line teams.
  • Join us to shape ADI's cutting-edge verification methods and take a leading role in driving excellence across digital DV practices!

    Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.

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