Responsibilities:
You will be responsible for understanding the analog-digital partition at system level, develop testplan for functional and circuit performance verification, testbench architecture, develop the scalable testbench using the HVLs, test case development, debugging, coverage model development, & coverage closure.
You will be working with analog circuit design team, digital design team, analog modeling, characterization team, controller subsystem team, & SoC integration team to complete the successful PHY level verification, integration into subsystem & SoC, & post-silicon validation. 
Minimum Qualifications :
Seeking candidates with combined 8-12 years of experience in digital design & verification (DV), test planning, problem solving, debug, adversarial testing, strong working knowledge of system verilog testbench, UVM methodology, Low power design concepts, Low power verification methodology, Verification of high speed parallel/serial IO interfaces such as D-PHY, M-PHY, SATA, Camera port, Display Port, PCIe, USB2.0, USB3.0, & HDMI, DDRPHY and/or DRAM controller, Well versed with JEDEC protocol for LPDDR2/3/4/5 & PCDDR2/3.
Education Requirements:
Required: Bachelor's, Computer Engineering and/or Computer Science and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Computer Science and/or Electrical Engineering